1. Field of the Invention
The present invention relates to a wiring board to mount a semiconductor element such as a semiconductor integrated circuit element.
2. Description of Related Art
Conventionally, according to a small-size wiring board to mount a semiconductor element, as shown in FIG. 6, a plurality of semiconductor element connection pads 22 are arranged in a center portion of an upper surface of an insulating board 21, and a plurality of external connection pads 23 are arranged in a whole region of a lower surface of the insulating board 21. In the insulating board 21, a plurality of buildup insulating layers 25 are laminated on each of upper and lower surfaces of a core insulating plate 24. A plurality of through-holes 26 are formed in the insulating plate 24. A plurality of via-holes 27 are formed in the insulating layer 25.
A core wiring conductor 28 is deposited on the upper and lower surfaces of the insulating plate 24 and an inner surface of the through-hole 26. A buildup wiring conductor 29 is deposited on a surface of each insulating layer 25 and an inner surface of the via-hole 27. The semiconductor element connection pad 22 is formed of the upper-side buildup wiring conductor 29 deposited on an outermost layer. The external connection pad 23 is formed of the lower-side buildup wiring conductor 29 deposited on an outermost layer. The semiconductor element connection pad 22 and the external connection pad 23 are electrically connected through the wiring conductors 28 and 29. The semiconductor element connection pads 22 and the external connection pads 23 are each divided into three kinds for a signal, the ground, and a power supply.
Furthermore, a solder resist layer 30 is deposited on the upper and lower surfaces of the insulating board 21. The upper-side solder resist layer 30 has openings 30a to expose center portions of the semiconductor element connection pads 22. The lower-side solder resist layer 30 has openings 30b to expose center portions of the external connection pads 23.
The conventional wiring board includes a differential transmission line for connecting the signal semiconductor element connection pad to the signal external connection pad as disclosed in Japanese Unexamined Patent Application Publication No. 2004-289094. This differential transmission line is schematically shown in FIG. 7. FIG. 7 only shows a part of the wiring conductors 28 and 29 required to describe the differential transmission line. The differential transmission line connects a pair of signal semiconductor element connection pads 22S adjacently arranged in the center portion of the upper surface of the insulating board 21, to a pair of signal external connection pads 23S adjacently arranged in an outer periphery portion of the lower surface of the insulating board 21, through a pair of adjacently arranged current paths.
The signal semiconductor element connection pads 22S are connected to one ends of a pair of thin strip-shaped wiring conductors 31. The strip-shaped wiring conductor 31 is formed on the upper-side insulating layer 25 so as to extend from the signal semiconductor element connection pad 22S to the outer periphery portion of the insulating board 21.
The pair of the signal external connection pads 23S are arranged along an extending direction of the strip-shaped wiring conductors 31, on the lower surface of the insulating board 21 under the other ends of the strip-shaped wiring conductors 31. The other ends of the strip-shaped wiring conductors 31 and the signal external connection pads 23S are connected through a pair of signal through-hole conductors 32S, upper-side signal connection conductors 33, and lower-side signal connection conductors 34. The signal through-hole conductor 32S is formed of the wiring conductor 28 deposited in the through-hole 26. The signal connection conductors 33 and 34 are formed of the wiring conductor 29 deposited on the surface of the insulating layer 25. The signal through-hole conductor 32S, and the signal connection conductors 33 and 34 are connected through a via conductor 35 (hereinafter, referred to as the “via-hole conductor” occasionally). The via conductor 35 is formed of the wiring conductor 29 deposited in the via-hole 27. The signal through-hole conductors 32S are arranged on a perpendicular line P which is perpendicular to the extending direction of the strip-shaped wiring conductor 31 so as to be opposed across a middle point between the pair of the signal external connection pads 23S.
A core ground conductor layer 36 is arranged on almost a whole region of the lower surface of the insulating plate 24. The core ground conductor layer 36 has an opening 36a which collectively surrounds lower ends of the pair of the signal through-hole conductors 32S. The opening 36a has an oblong shape which is long in the direction of the perpendicular line P. The insulating plate 24 has a pair of ground through-hole conductors 32G provided so as to be adjacent to the pair of the signal through-hole conductors 32S. The ground through-hole conductors 32G are adjacently arranged on one side of the opening 36a, and their lower ends are connected to the core ground conductor layer 36.
A pair of ground external connection pads 23G is arranged on the lower surface of the insulating board 21 so as to be adjacent to the pair of the signal external connection pads 23S, along the extending direction of the strip-shaped wiring conductor 31. These ground external connection pads 23G are connected to the core ground conductor layer 36 through the via-hole conductors 35.
The upper-side insulating layer 25 has a buildup ground conductor layer (not shown) so as to be opposed to the strip-shaped wiring conductor 31, that is, arranged on the left, right, top, and bottom of the strip-shaped wiring conductor 31. The ground through-hole conductor 32G is connected to the buildup ground conductor layer through the via-hole conductor 35.
According to the conventional wiring board, when a signal is transmitted to the differential transmission line which connects the signal semiconductor element connection pad 22S to the signal external connection pad 23S, a return current flows through the ground through-hole conductor 32G so as to correspond to the signal which is transmitted in the differential transmission line from the buildup ground conductor layer provided on the left, right, top, and bottom of the strip-shaped wiring conductor 31 to the ground external connection pad 23G.
However, according to the conventional wiring board, when the signal is transmitted to the differential transmission line to connect the signal semiconductor element connection pad 22S to the signal external connection pad 23S, a small time lag is generated in transmitting the signal between the pair of the current paths to connect them. When this time lag exceeds 1.0 picosecond (ps) in a case where a transmission rate of the signal transmitted in the differential transmission line is as high as 25 Gbps or more, for example, the semiconductor element to be mounted cannot sufficiently achieve its performance, or is likely to generate a malfunction. Therefore, in the case where the transmission rate of the signal transmitted in the differential transmission line is as high as 25 Gbps or more, the time lag in signal transmission between the pair of the current paths is preferably 0.2 ps or less so that the semiconductor element to be mounted can be easily operated with sufficient performance and accuracy.
Thus, the differential transmission line to connect the signal semiconductor element connection pads 22S to the signal external connection pads 23S is designed so that the lengths of the pair of the current paths to connect them become equal to each other as much as possible. However, even when the lengths of the pair of the current paths in the differential transmission line are made equal to each other, it is extremely difficult to reduce the time lag in signal transmission between the current paths to 0.2 ps or less. Thus, the present inventor focused on and studied a return current which flows in response to the signal transmitted in the differential transmission line.
Here, FIG. 8 schematically shows flows of the return currents from the ground external connection pad 23G to the ground through-hole conductor 32G. FIG. 8 only shows a part of the wiring conductors 28 and 29 under the through-hole conductors 32S and 32G. In addition, the flow of the return current is shown by an arrow. First, the return current flows from the ground external connection pad 23G to the ground conductor layer 36 through the via-hole conductor 35. In the ground conductor layer 36, the return current flows from a portion connected to the via-hole conductor 35 to the ground through-hole conductor 32G. At this time, it is found that there is a difference in length between the current paths of the return currents on both sides provided across the perpendicular line P from each other.
It is considered that this difference in length between the current paths of the return currents affects the time lag in signal transmission between the pair of the current paths in the differential transmission line to connect the signal semiconductor element connection pad 22S to the signal external connection pad 23S. In addition, it is considered that as for the current path shown by a dotted line arrow, the opening 36a hinders a favorable flow of the return current, so that the return current is not likely to sufficiently flow.